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ai01372 19 a0-a18 w dq0-dq7 v cc M29F040 g e v ss 8 figure 1. logic diagram M29F040 4 mbit (512kb x8, uniform block) single supply flash memory not for new design M29F040 is replaced by the M29F040b 5v 10% supply voltage for program, erase and read operations fast access time: 70ns byte programming time: 10 m s typical erase time C block: 1.0 sec typical C chip: 2.5 sec typical program/erase controller (p/e.c.) C program byte-by-byte C data polling and toggle bits protocol for p/e.c. status memory erase in blocks C 8 uniform blocks of 64 kbytes each C block protection C multiblock erase erase suspend and resume modes low power consumption C read mode: 8ma typical (at 12mhz) C stand-by mode: 25 m a typical C automatic stand-by mode 100,000 program/erase cycles per block 20 years data retention C defectivity below 1ppm/year electronic signature C manufacturer code: 20h C device code: e2h a0-a18 address inputs dq0-dq7 data input / outputs e chip enable g output enable w write enable v cc supply voltage v ss ground table 1. signal names plcc32 (k) tsop32 (n) 8 x 20 mm november 1999 1/31 this is information on a product still in production but not recommended for new designs.
a1 a0 dq0 a7 a4 a3 a2 a6 a5 a13 a10 a8 a9 dq7 a14 a11 g e dq5 dq1 dq2 dq3 dq4 dq6 a17 w a16 a12 a18 v cc a15 ai01379 M29F040 (normal) 8 1 9 16 17 24 25 32 v ss figure 2b. tsop pin connections ai01378 a17 a13 a10 dq5 17 a1 a0 dq0 dq1 dq2 dq3 dq4 a7 a4 a3 a2 a6 a5 9 w a8 1 a16 a9 dq7 a12 a14 32 a18 v cc M29F040 a15 a11 dq6 g e 25 v ss figure 2a. lcc pin connections a1 a0 dq0 a7 a4 a3 a2 a6 a5 a13 a10 a8 a9 dq7 a14 a11 g e dq5 dq1 dq2 dq3 dq4 dq6 a17 w a16 a12 a18 v cc a15 ai01174b M29F040 (reverse) 8 1 9 16 17 24 25 32 v ss figure 2c. tsop reverse pin connections description the M29F040 is a non-volatile memory that may be erased electrically at the block level, and pro- grammed byte-by-byte. the interface is directly compatible with most mi- croprocessors. plcc32 and tsop32 (8 x 20mm) packages are available. both normal and reverse pin outs are available for the tsop32 package. organisation the flash memory organisation is 512k x8 bits with address lines a0-a18 and data inputs/outputs dq0-dq7. memory control is provided by chip enable, output enable and write enable inputs. erase and program are performed through the internal program/erase controller (p/e.c.). data outputs bits dq7 and dq6 provide polling or toggle signals during automatic program or erase to indicate the ready/busy state of the internal program/erase controller. memory blocks erasure of the memory is in blocks. there are 8 uniform blocks of 64 kbytes each in the memory address space. each block can be programmed and erased over 100,000 cycles. each uniform block may separately be protected and unpro- 2/31 M29F040
symbol parameter value unit t a ambient operating temperature (3) C40 to 125 c t bias temperature under bias C50 to 125 c t stg storage temperature C65 to 150 c v io (2) input or output voltages C0.6 to 7 v v cc supply voltage C0.6 to 7 v v a9 (2) a9 voltage C0.6 to 13.5 v notes: 1. except for the rating "operating temperature range", stresses above those listed in the table "absolute maximum ratings" may cause permanent damage to the device. these are stress ratings only and operation of the device at these or any other conditions above those indicated in the operating sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliab ility. refer also to the stmicroelectronics sure program and other relevant quality documents. 2. minimum voltage may undershoot to C2v during transition and for less than 20ns. 3. depends on range. table 2. absolute maximum ratings (1) tected against program and erase. block erasure may be suspended, while data is read from other blocks of the memory, and then resumed. bus operations seven operations can be performed by the appro- priate bus cycles, read array, read electronic signature, output disable, standby, protect block, unprotect block, and write the command of an instruction. command interface command bytes can be written to a command interface (c.i.) latch to perform reading (from the array or electronic signature), erasure or pro- gramming. for added data protection, command execution starts after 4 or 6 command cycles. the first, second, fourth and fifth cycles are used to input a code sequence to the command interface (c.i.). this sequence is equal for all p/e.c. instruc- tions. command itself and its confirmation - if it applies - are given on the third and fourth or sixth cycles. instructions seven instructions are defined to perform reset, read electronic signature, auto program, block auto erase, chip auto erase, block erase suspend and block erase resume. the internal pro- gram/erase controller (p/e.c.) handles all timing and verification of the program and erase instruc- tions and provides data polling, toggle, and status data to indicate completion of program and erase operations. instructions are composed of up to six cycles. the first two cycles input a code sequence to the com- mand interface which is common to all p/e.c. instructions (see table 7 for command descrip- tions). the third cycle inputs the instruction set up command instruction to the command interface. subsequent cycles output signature, block protec- tion or the addressed data for read operations. for added data protection, the instructions for pro- gram, and block or chip erase require further com- mand inputs. for a program instruction, the fourth command cycle inputs the address and data to be programmed. for an erase instruction (block or chip), the fourth and fifth cycles input a further code sequence before the erase confirm command on the sixth cycle. byte programming takes typically 10 m s while erase is performed in typically 1.0 sec- ond. erasure of a memory block may be suspended, in order to read data from another block, and then resumed. data polling, toggle and error data may be read at any time, including during the program- ming or erase cycles, to monitor the progress of the operation. when power is first applied or if v cc falls below v lko , the command interface is reset to read array. 3/31 M29F040
operation e g w dq0 - dq7 read v il v il v ih data output write v il v ih v il data input output disable v il v ih v ih hi-z standby v ih x x hi-z note: x = v il or v ih table 3. operations code e g w a0a1a6a9 other addresses dq0 - dq7 manufact. code v il v il v ih v il v il v il v id dont care 20h device code v il v il v ih v ih v il v il v id dont care e2h table 4. electronic signature code e g w a0 a1 a6 a16 a17 a18 other addresses dq0 - dq7 protected block v il v il v ih v il v ih v il sa sa sa dont care 01h unprotected block v il v il v ih v il v ih v il sa sa sa dont care 00h note: sa = address of block being checked table 5. block protection status device operation signal descriptions address inputs (a0-a18). the address inputs for the memory array are latched during a write opera- tion. the a9 address input is used also for the electronic signature read and block protect veri- fication. when a9 is raised to v id , either a read manufacturer code, read device code or verify block protection is enabled depending on the com- bination of levels on a0, a1 and a6. when a0, a1 and a6 are low, the electronic signature manufac- turer code is read, when a0 is high and a1 and a6 are low, the device code is read, and when a1 is high and a0 and a6 are low, the block protection status is read for the block addressed by a16, a17, a18. data input/outputs (dq0-dq7). the data input is a byte to be programmed or a command written to the c.i. both are latched when chip enable e and write enable w are active. the data output is from the memory array, the electronic signature, the data polling bit (dq7), the toggle bit (dq6), the error bit (dq5) or the erase timer bit (dq3). ou- puts are valid when chip enable e and output enable g are active. the output is high impedance when the chip is deselected or the outputs are disabled. chip enable ( e). the chip enable activates the memory control logic, input buffers, decoders and sense amplifiers. e high deselects the memory and reduces the power consumption to the standby level. e can also be used to control writing to the command register and to the memory array, while w remains at a low level. addresses are then latched on the falling edge of e while data is latched on the rising edge of e. the chip enable must be forced to v id during block unprotect operations. output enable ( g). the output enable gates the outputs through the data buffers during a read operation. g must be forced to v id level during block protect and block unprotect operations. write enable ( w). this input controls writing to the command register and address and data latches. addresses are latched on the falling edge of w, and data inputs are latched on the rising edge of w. v cc supply voltage. the power supply for all operations (read, program and erase). v ss ground. v ss is the reference for all voltage measurements. 4/31 M29F040
mne. instr. cyc. 1st cyc. 2nd cyc. 3rd cyc. 4th cyc. 5th cyc. 6th cyc. 7th cyc. rst (4,10) read array/ reset 1+ addr. (3,7) x read memory array until a new write cycle is initiated. data f0h 3+ addr. (3,7) 5555h 2aaah 5555h read memory array until a new write cycle is initiated. data aah 55h f0h rsig (4) read electronic signature 3+ addr. (3,7) 5555h 2aaah 5555h read electronic signature until a new write cycle is initiated. see note 5. data aah 55h 90h rbp (4) read block protection 3+ addr. (3,7) 5555h 2aaah 5555h read block protection until a new write cycle is initiated. see note 6. data aah 55h 90h pg program 4 addr. (3,7) 5555h 2aaah 5555h program address read data polling or toggle bit until program completes. data aah 55h a0h program data be block erase 6 addr. (3,7) 5555h 2aaah 5555h 5555h 2aaah block address additional block (8) data aah 55h 80h aah 55h 30h 30h ce chip erase 6 addr. (3,7) 5555h 2aaah 5555h 5555h 2aaah 5555h note 9 data aah 55h 80h aah 55h 10h es erase suspend 1 addr. (3,7) x read until toggle stops, then read all the data needed from any uniform block(s) not being erased then resume erase. data b0h er erase resume 1 addr. (3,7) x read data polling or toggle bit until erase completes or erase is suspended another time data 30h notes: 1. command not interpreted in this table w ill default to r ead array mode. 2. while writing any command or during rsg and rsp execution, the p/e.c. can be reset by writing the command 00h to the c.i. 3. x = dont care. 4. the first cycle of the rst, rbp or rsig instruction is followed by read operations to read memory array, status register or electronic signature codes. any number of read cycles can occur after one command cycle. 5. signature address bits a0, a1, a6 at v il will output manufacturer code (20h). address bits a0 at v ih and a1, a6 at v il will output device code. 6. protection address: a0, a6 at v il , a1 at v ih and a16, a17, a18 within the uniform block to be checked, will output the block protection status. 7. address bits a15-a18 are dont care for coded address inputs. 8. optional, additional blocks addresses must be entered within a 80 m s delay after last write entry, timeout status can be verified through dq3 value. when full command is entered, read data polling or toggle bit until erase is completed or suspended. 9. read data polling or toggle bit until erase completes. 10. a wait time of 5 m s is necessary after a reset command, if the memory is in a block erase status, before starting any operation. table 6. instructions (1,2) 5/31 M29F040
memory blocks the memory blocks of the M29F040 are shown in figure 3. the memory array is divided in 8 uniform blocks of 64 kbytes. each block can be erased separately or any combination of blocks can be erased simultaneously. the block erase operation is managed automatically by the p/e.c. the opera- tion can be suspended in order to read from any other block, and then resumed. block protection provides additional data security. each uniform block can be separately protected or unprotected against program or erase. bringing a9 and g to v id initiates protection, while bringing a9, g and e to v id cancels the protection. the block affected during protection is addressed by the in- puts on a16, a17, and a18. unprotect operation affects all blocks. operations operations are defined as specific bus cycles and signals which allow memory read, command write, output disable, standby, read status bits, block protect/unprotect, block protection check and electronic signature read. they are shown in tables 3, 4, 5. read. read operations are used to output the contents of the memory array, the status register or the electronic signature. both chip enable e and output enable g must be low in order to read the output of the memory. the chip enable input also provides power control and should be used for device selection. output enable should be used to gate data onto the output independent of the device selection. the data read depends on the previous command written to the memory (see instructions rst and rsig, and status bits). write. write operations are used to give instruction commands to the memory or to latch input data to be programmed. a write operation is initiated when chip enable e is low and write enable w is low with output enable g high. addresses are latched on the falling edge of w or e whichever occurs last. commands and input data are latched on the rising edge of w or e whichever occurs first. output disable. the data outputs are high imped- ance when the output enable g is high with write enable w high. standby. the memory is in standby when chip enable e is high and program/erase controller p/e.c. is idle. the power consumption is reduced to the standby level and the outputs are high im- pedance, independent of the output enable g or write enable w inputs. automatic standby. after 150ns of inactivity and when cmos levels are driving the addresses, the chip automatically enters a pseudo standby mode where consumption is reduced to the cmos standby value, while outputs are still driving the bus. electronic signature. two codes identifying the manufacturer and the device can be read from the memory, the manufacturers code for stmicroelec- tronics is 20h, and the device code is e2h for the M29F040. these codes allow programming equip- ment or applications to automatically match their interface to the characteristics of the particular manufacturers product. the electronic signature is output by a read operation when the voltage applied to a9 is at v id and address inputs a1 and a6 are at low. the manufacturer code is output when the address input a0 is low and the device code when this input is high. other address inputs are ignored. the codes are output on dq0-dq7. this is shown in table 4. the electronic signature can also be read, without raising a9 to v id by giving the memory the instruc- tion rsig (see below). block protection. each uniform block can be separately protected against program or erase. block protection provides additional data security, as it disables all program or erase operations. this mode is activated when both a9 and g are set to v id and the block address is applied on a16-a18. block protection is programmed using a presto f program like algorithm. protection is initiated on the edge of w falling to v il . then after a delay of 100 m s, the edge of w rising to v ih ends the protection operation. protection verify is achieved by bringing g, e and a6 to v il while w is at v ih and a9 at v id . under these conditions, reading the data output will yield 01h if the block defined by the inputs on a16-a18 is protected. any attempt to program or erase a protected block will be ignored by the device. any protected block can be unprotected to allow updating of bit contents. all blocks must be pro- tected before an unprotect operation. block un- protect is activated when a9, g and e are at v id . the addresses inputs a6, a12, a16 must be main- tained at v ih . block unprotect is performed through a presto f erase like algorithm. unprotect is initi- ated by the edge of w falling to v il . after a delay of 10ms, the edge of w rising to v ih will end the unprotection operation. unprotect verify is achieved by bringing g and e to v il while a6 and w are at v ih and a9 at v id . in these conditions, reading the output data will yield 00h if the block defined by the inputs on a16-a18 has been suc- cessfully unprotected. all combinations of a16- a18 must be addressed in order to ensure that all of the 8 uniform blocks have been unprotected. block protection status is shown in table 5. 6/31 M29F040
64k bytes block ai01362b 7ffffh 6ffffh 5ffffh 4ffffh 3ffffh 2ffffh 1ffffh 0ffffh top address 70000h 60000h 50000h 40000h 30000h 20000h 10000h 00000h bottom address a18 1 1 64k bytes block 64k bytes block 64k bytes block 64k bytes block a17 1 1 a16 1 0 1 1 0 0 1 0 0 0 1 1 1 0 001 000 figure 3. memory map and block address table hex code command 00h read 10h chip erase confirm 30h block erase resume/confirm 80h set-up erase 90h read electronic signature/ block protection status a0h program b0h erase suspend f0h read array/reset table 7. commands instructions and commands the command interface (c.i.) latches commands written to the memory. instructions are made up from one or more commands to perform read array/reset, read electronic signature, block erase, chip erase, program, block erase suspend and erase resume. commands are made of ad- dress and data sequences. addresses are latched on the falling edge of w or e and data is latched on the rising of w or e. the instructions require from 1 to 6 cycles, the first or first three of which are always write operations used to initiate the com- mand. they are followed by either further write cycles to confirm the first command or execute the command immediately. command sequencing must be followed exactly. any invalid combination of commands will reset the device to read array. the increased number of cycles has been chosen to assure maximum data security. commands are initialised by two preceding coded cycles which unlock the command interface. in addition, for erase, command confirmation is again preceeded by the two coded cycles. p/e.c. status is indicated during command execu- tion by data polling on dq7, detection of toggle on dq6, or error on dq5 and erase timer dq3 bits. any read attempt during program or erase com- mand execution will automatically output those four bits. the p/e.c. automatically sets bits dq3, dq5, dq6 and dq7. other bits (dq0, dq1, dq2 and dq4) are reserved for future use and should be masked. 7/31 M29F040
dq name logic level definition note 7 data polling 1 erase complete indicates the p/e.c. status, check during program or erase, and on completion before checking bits dq5 for program or erase success. 0 erase on going dq program complete dq program on going 6 toggle bit -1-0-1-0-1-0-1- erase or program on going successive read output complementary data on dq6 while programming or erase operations are going on. dq6 remain at constant level when p/e.c. operations are completed or erase suspend is acknowledged. -0-0-0-0-0-0-0- program (0 on dq6) complete -1-1-1-1-1-1-1- erase or program (1 on dq6) complete 5 error bit 1 program or erase error this bit is set to 1 if p/e.c. has exceded the specified time limits. 0 program or erase on going 4 1 0 3 erase time bit 1 erase timeout period expired p/e.c. erase operation has started. only possible command entry is erase suspend (es). an additional block to be erased in parallel can be entered to the p/e.c. 0 erase timeout period on going 2 reserved 1 reserved 0 reserved note: logic level 1 is high, 0 is low. -0-1-0-0-0-1-1-1-0- represent bit value in successive read operations. table 8. status register data polling bit (dq7). when programming op- erations are in progress, this bit outputs the com- plement of the bit being programmed on dq7. during erase operation, it outputs a 0. after com- pletion of the operation, dq7 will output the bit last programmed or a 1 after erasing. data polling is valid only effective during p/e.c. operation, that is after the fourth w pulse for programming or after the sixth w pulse for erase. it must be performed at the address being programmed or at an address within the block being erased. if the byte to be programmed belongs to a protected block the com- mand is ignored. if all the blocks selected for era- sure are protected, dq7 will set to 0 for about 100 m s, and then return to previous addressed memory data. see figure 9 for the data polling flowchart and figure 10 for the data polling wave- forms. toggle bit (dq6). when programming operations are in progress, successive attempts to read dq6 will output complementary data. dq6 will toggle following toggling of either g or e when g is low. the operation is completed when two successive reads yield the same output data. the next read will output the bit last programmed or a 1 after erasing. the toggle bit is valid only effective during p/e.c. operations, that is after the fourth w pulse for programming or after the sixth w pulse for erase. if the byte to be programmed belongs to a protected block the command will be ignored. if the blocks selected for erasure are protected, dq6 will toggle for about 100 m s and then return back to read. see figure 11 for toggle bit flowchart and figure 12 for toggle bit waveforms. error bit (dq5). this bit is set to 1 by the p/e.c when there is a failure of byte programming, block erase, or chip erase that results in invalid data being programmed in the memory block. in case of error in block erase or byte program, the block in which the error occured or to which the pro- grammed byte belongs, must be discarded. other blocks may still be used. error bit resets after reset (rst) instruction. in case of success, the error bit will set to 0 during program or erase and to valid data after write operation is completed. 8/31 M29F040
ai01275b 3v high speed 0v 1.5v 2.4v standard 0.45v 2.0v 0.8v figure 4. ac testing input output waveform ai01276b 1.3v out c l c l = 30pf for high speed c l = 100pf for standard c l includes jig capacitance 3.3k w 1n914 device under test figure 5. ac testing load circuit symbol parameter test condition min max unit c in input capacitance v in = 0v 6 pf c out output capacitance v out = 0v 12 pf note: 1. sampled only, not 100% tested. table 10. capacitance (1) (t a = 25 c, f = 1 mhz ) erase timer bit (dq3). this bit is set to 0 by the p/e.c. when the last block erase command has been entered to the command interface and it is awaiting the erase start. when the wait period is finished, after 80 to 120 m s, dq3 returns back to 1. coded cycles. the two coded cycles unlock the command interface. they are followed by a com- mand input or a comand confirmation. the coded cycles consist of writing the data aah at address 5555h during the first cycle and data 55h at address 2aaah during the second cycle. addresses are latched on the falling edge of w or e while data is latched on the rising edge of w or e. the coded cycles happen on first and second cycles of the command write or on the fourth and fifth cycles. read array/reset (rst) instruction. the reset instruction consists of one write operation giving the command f0h. it can be optionally preceded by the two coded cycles. a wait state of 5 m s before read operations is necessary if the reset command is applied during an erase operation. read electronic signature (rsig) instruction. this instruction uses the two coded cycles followed by one write cycle giving the command 90h to address 5555h for command setup. a subsequent read will output the manufacturer code, the device code or the block protection status depending on the levels of a0, a1, a6, a16, a17 and a18. the manufacturer code, 20h, is output when the ad- dresses lines a0, a1 and a6 are low, the device code, e2h is output when a0 is high with a1 and a6 low. high speed standard input rise and fall times 10ns 10ns input pulse voltages 0 to 3v 0.45v to 2.4v input and output timing ref. voltages 1.5v 0.8v and 2v table 9. ac measurement conditions 9/31 M29F040
symbol parameter test condition min max unit i li input leakage current 0v v in v cc 1 m a i lo output leakage current 0v v out v cc 1 m a i cc1 supply current (read) e = v il , g = v ih , f = 6mhz 15 ma i cc2 supply current (standby) ttl e = v ih 1ma i cc3 supply current (standby) cmos e = v cc 0.2v 50 m a i cc4 supply current (program or erase) byte program, block erase 20 ma i cc5 supply current chip erase in progress 40 ma v il input low voltage C0.5 0.8 v v ih input high voltage 2 v cc + 0.5 v v ol output low voltage i ol = 10ma 0.45 v v oh output high voltage ttl i oh = C2.5ma 2.4 v output high voltage cmos i oh = C100 m av cc C0.4 v i oh = C2.5ma 0.85 v cc v v id a9 voltage (electronic signature) 11.5 12.5 v i id a9 current (electronic signature) a9 = v id 50 m a v lko supply voltage (erase and program lock-out) 3.2 4.2 v table 11. dc characteristics (t a = 0 to 70 c, C20 to 85 c, C40 to 85 c or C40 to 125 c; v cc = 5v 10%) read block protection (rbp) instruction. the use of read electronic signature (rsig) command also allows access to the block protection status verify. after giving the rsig command, a0 and a6 are set to v il with a1 at v ih , while a16, a17 and a18 define the block of the block to be verified. a read in these conditions will output a 01h if block is protected and a 00h if block is not protected. this read block protection is the only valid way to check the protection status of a block. neverthe- less, it must not be used during the block protection phase as a method to verify the block protection. please refer to block protection paragraph. chip erase (ce) instruction. this instruction uses six write cycles. the erase set-up command 80h is written to address 5555h on third cycle after the two coded cycles. the chip erase confirm com- mand 10h is written at address 5555h on sixth cycle after another two coded cycles. if the second com- mand given is not an erase confirm or if the coded cycles are wrong, the instruction aborts and the device is reset to read array. it is not necessary to program the array with 00h first as the p/e.c. will automatically do this before erasing to ffh. read operations after the sixth rising edge of w or e output the status register bits. during the execu- tion of the erase by the p/e.c. the memory accepts only the reset (rst) command. read of data polling bit dq7 returns 0, then 1 on completion. the toggle bit dq6 toggles during erase operation and stops when erase is completed. after comple- tion the status register bit dq5 returns 1 if there has been an erase failure because the erasure has not been verified even after the maximum number of erase cycles have been executed. 10/31 M29F040
symbol alt parameter test condition M29F040 unit -70 -90 v cc = 5v 5% v cc = 5v 10% standard interface standard interface min max min max t avav t rc address valid to next address valid e = v il , g = v il 70 90 ns t avqv t acc address valid to output valid e = v il , g = v il 70 90 ns t elqx (1) t lz chip enable low to output transition g = v il 00ns t elqv (2) t ce chip enable low to output valid g = v il 70 90 ns t glqx (1) t olz output enable low to output transition e = v il 00ns t glqv (2) t oe output enable low to output valid e = v il 30 35 ns t ehqx t oh chip enable high to output transition g = v il 00ns t ehqz (1) t hz chip enable high to output hi-z g = v il 20 20 ns t ghqx t oh output enable high to output transition e = v il 00ns t ghqz (1) t df output enable high to output hi-z e = v il 20 20 ns t axqx t oh address transition to output transition e = v il , g = v il 20 20 ns notes: 1. sampled only, not 100% tested. 2. g may be delayed by up to t elqv - t glqv after the falling edge of e without increasing t elqv . 3. the temperature range C40 to 125 c is guaranteed at 70ns with high speed interface test condition and v cc = 5v 5%. table 12a. read ac characteristics (t a = 0 to 70 c, C20 to 85 c, C40 to 85 c or C40 to 125 c) (3) block erase (be) instruction . this instruction uses a minimum of six write cycles. the erase set-up command 80h is written to address 5555h on third cycle after the two coded cycles. the block erase confirm command 30h is written on sixth cycle after another two coded cycles. during the input of the second command an address within the block to be erased is given and latched into the memory. additional block erase confirm com- mands and block addresses can be written sub- sequently to erase other blocks in parallel, without further coded cycles. the erase will start after an erase timeout period of about 100 m s. thus, addi- tional block erase commands must be given within this delay. the input of a new block erase com- mand will restart the timeout period. the status of the internal timer can be monitored through the level of dq3, if dq3 is 0 the block erase com- mand has been given and the timeout is running, if dq3 is 1, the timeout has expired and the p/e.c is erasing the block(s). before and during erase timeout, any command different from 30h will abort the instruction and reset the device to read array mode. it is not necessary to program the block with 00h as the p/e.c. will do this automatically before erasing to ffh. read operations after the sixth rising edge of w or e output the status register bits. during the execution of the erase by the p/e.c., the memory accepts only the es (erase suspend) and rst (reset) instructions. data polling bit dq7 returns 0 while the erasure is in progress and 1 when it has completed. the toggle bit dq6 toggles during the erase operation. it stops when erase is completed. after completion the status register bit dq5 returns 1 if there has been an erase failure because erasure has not completed even after the maximum number of erase cycles have been executed. in this case, it will be necessary to input a reset (rst) to the command interface in order to reset the p/e.c. 11/31 M29F040
symbol alt parameter test condition M29F040 unit -120 -150 v cc = 5v 10% v cc = 5v 10% standard interface standard interface min max min max t avav t rc address valid to next address valid e = v il , g = v il 120 150 ns t avqv t acc address valid to output valid e = v il , g = v il 120 150 ns t elqx (1) t lz chip enable low to output transition g = v il 00ns t elqv (2) t ce chip enable low to output valid g = v il 120 150 ns t glqx (1) t olz output enable low to output transition e = v il 00ns t glqv (2) t oe output enable low to output valid e = v il 50 55 ns t ehqx t oh chip enable high to output transition g = v il 00ns t ehqz (1) t hz chip enable high to output hi-z g = v il 30 35 ns t ghqx t oh output enable high to output transition e = v il 00ns t ghqz (1) t df output enable high to output hi-z e = v il 30 35 ns t axqx t oh address transition to output transition e = v il , g = v il 20 20 ns notes: 1. sampled only, not 100% tested. 2. g may be delayed by up to t elqv - t glqv after the falling edge of e without increasing t elqv . table 12b. read ac characteristics (t a = 0 to 70 c, C20 to 85 c, C40 to 85 c or C40 to 125 c) program (pg) instruction. the memory can be programmed byte-by-byte. this instruction uses four write cycles. the program command a0h is written on the third cycle after two coded cycles. a fourth write operation latches the address on the falling edge of w or e and the data to be written on its rising edge and starts the p/e.c. during the execution of the program by the p/e.c., the mem- ory will not accept any instruction. read operations output the status bits after the programming has started. the status bits dq5, dq6 and dq7 allow a check of the status of the programming operation. memory programming is made only by writing 0 in place of 1 in a byte. erase suspend (es) instruction. the block erase operation may be suspended by this instruc- tion which consists of writing the command 0b0h without any specific address code. no coded cycles are required. it allows reading of data from another block while erase is in progress. erase suspend is accepted only during the block erase instruction execution and defaults to read array mode. writing this command during erase timeout will, in addition to suspending the erase, terminate the timeout. the toggle bit dq6 stops toggling when the p/e.c. is suspended. toggle bit status must be monitored at an address out of the block being erased. toggle bit will stop toggling between 0.1 m s and 15 m s after the erase suspend (es) command has been writ- ten. the M29F040 will then automatically set to read memory array mode. when erase is suspended, read from blocks being erased will output invalid data, read from block not being erased is valid. during the suspension the memory will respond only to erase resume (er) and reset (rst) in- structions. rst command will definitively abort erasure and result in the invalid data in the blocks being erased. 12/31 M29F040
ai01363b tavav tavqv taxqx telqx tehqz tglqv tglqx tghqx valid a0-a18 e g dq0-dq7 telqv valid address valid and chip enable output enable data valid tehqx tghqz figure 6. read mode ac waveforms note: write enable ( w) = high 13/31 M29F040
symbol alt parameter M29F040 unit -70 -90 v cc = 5v 10% v cc = 5v 10% standard interface standard interface min max min max t avav t wc address valid to next address valid 70 90 ns t elwl t cs chip enable low to write enable low 0 0 ns t wlwh t wp write enable low to write enable high 35 45 ns t dvwh t ds input valid to write enable high 30 45 ns t whdx t dh write enable high to input transition 0 0 ns t wheh t ch write enable high to chip enable high 0 0 ns t whwl t wph write enable high to write enable low 20 20 ns t avwl t as address valid to write enable low 0 0 ns t wlax t ah write enable low to address transition 45 45 ns t ghwl output enable high to write enable low 0 0 ns t vchel t vcs v cc high to chip enable low 50 50 m s t whqv1 (1) write enable high to output valid (program) 10 10 m s t whqv2 (1) write enable high to output valid (block erase) 1.0 30 1.0 30 sec t whgl t oeh write enable high to output enable low 0 0 ns note: 1. time is measured to data polling or toggle bit, t whqv = t whq7v + t q7vqv 2. the temperature range C40 to 125 c is guaranteed at 70ns with high speed interface test condition and v cc = 5v 5%. table 13a. write ac characteristics, write enable controlled (t a = 0 to 70 c, C20 to 85 c, C40 to 85 c or C40 to 125 c) (2) erase resume (er) instruction. if an erase sus- pend instruction was previously executed, the erase operation may be resumed by giving the command 30h, at any address, and without any coded cycles. power up the memory command interface is reset on power up to read array. either e or w must be tied to v ih during power-up to allow maximum security and the possibility to write a command on the first rising adge of e or w. any write cycle initiation is blocked when v cc is below v lko . supply rails normal precautions must be taken for supply volt- age decoupling, each device in a system should have the v cc rail decoupled with a 1.0 m f capacitor close to the v cc and v ss pins. the pcb trace widths should be sufficient to carry the v cc pro- gram and erase currents required. 14/31 M29F040
symbol alt parameter M29F040 unit -120 -150 v cc = 5v 10% v cc = 5v 10% standard interface standard interface min max min max t avav t wc address valid to next address valid 120 150 ns t elwl t cs chip enable low to write enable low 0 0 ns t wlwh t wp write enable low to write enable high 50 50 ns t dvwh t ds input valid to write enable high 50 50 ns t whdx t dh write enable high to input transition 0 0 ns t wheh t ch write enable high to chip enable high 0 0 ns t whwl t wph write enable high to write enable low 20 20 ns t avwl t as address valid to write enable low 0 0 ns t wlax t ah write enable low to address transition 50 50 ns t ghwl output enable high to write enable low 0 0 ns t vchel t vcs v cc high to chip enable low 50 50 m s t whqv1 (1) write enable high to output valid (program) 10 10 m s t whqv2 (1) write enable high to output valid (block erase) 1.0 30 1.0 30 sec t whgl t oeh write enable high to output enable low 0 0 ns note: 1. time is measured to data polling or toggle bit, t whqv = t whq7v + t q7vqv table 13b. write ac characteristics, write enable controlled (t a = 0 to 70 c, C20 to 85 c, C40 to 85 c or C40 to 125 c) 15/31 M29F040
ai01365b e g w a0-a18 dq0-dq7 valid valid v cc tvchel twheh twhwl telwl tavwl twhgl twlax twhdx write cycle tdvwh twlwh tghwl figure 7. write ac waveforms, w controlled note: address are latched on the fa lling edge of w, data is latched on the rising edge of w. 16/31 M29F040
symbol alt parameter M29F040 unit -70 -90 v cc = 5v 10% v cc = 5v 10% standard interface standard interface min max min max t avav t wc address valid to next address valid 70 90 ns t wlel t ws write enable low to chip enable low 0 0 ns t eleh t cp chip enable low to chip enable high 35 45 ns t dveh t ds input valid to chip enable high 30 45 ns t ehdx t dh chip enable high to input transition 0 0 ns t ehwh t wh chip enable high to write enable high 0 0 ns t ehel t cph chip enable high to chip enable low 20 20 ns t avel t as address valid to chip enable low 0 0 ns t elax t ah chip enable low to address transition 45 45 ns t ghel output enable high chip enable low 0 0 ns t vchwl t vcs v cc high to write enable low 50 50 m s t ehqv1 (1) chip enable high to output valid (program) 10 10 m s t ehqv2 (1) chip enable high to output valid (block erase) 1.0301.030sec t ehgl t oeh chip enable high to output enable low 0 0 ns note: 1. time is measured to data polling or toggle bit, t whqv = t whq7v + t q7vqv . 2. the temperature range C40 to 125 c is guaranteed at 70ns with high speed interface test condition and v cc = 5v 5%. table 14a. write ac characteristics, chip enable controlled (t a = 0 to 70 c, C20 to 85 c, C40 to 85 c or C40 to 125 c) (2) 17/31 M29F040
symbol alt parameter M29F040 unit -120 -150 v cc = 5v 10% v cc = 5v 10% standard interface standard interface min max min max t avav t wc address valid to next address valid 120 150 ns t wlel t ws write enable low to chip enable low 0 0 ns t eleh t cp chip enable low to chip enable high 50 50 ns t dveh t ds input valid to chip enable high 50 50 ns t ehdx t dh chip enable high to input transition 0 0 ns t ehwh t wh chip enable high to write enable high 0 0 ns t ehel t cph chip enable high to chip enable low 20 20 ns t avel t as address valid to chip enable low 0 0 ns t elax t ah chip enable low to address transition 50 50 ns t ghel output enable high chip enable low 0 0 ns t vchwl t vcs v cc high to write enable low 50 50 m s t ehqv1 (1) chip enable high to output valid (program) 10 10 m s t ehqv2 (1) chip enable high to output valid (block erase) 1.0 30 1.0 30 sec t ehgl t oeh chip enable high to output enable low 0 0 ns note: 1. time is measured to data polling or toggle bit, t whqv = t whq7v + t q7vqv . table 14b. write ac characteristics, chip enable controlled (t a = 0 to 70 c, C20 to 85 c, C40 to 85 c or C40 to 125 c) 18/31 M29F040
ai01366b e g w a0-a18 dq0-dq7 valid valid v cc tvchwl tehwh tehel twlel tavel tehgl telax tehdx write cycle tdveh teleh tghel figure 8. write ac waveforms, e controlled note: address are latched on the falling edge of e, data is latched on the rising edge of e. 19/31 M29F040
symbol parameter M29F040 unit -70 -90 v cc = 5v 10% v cc = 5v 10% standard interface standard interface min max min max t whq7v1 (2) write enable high to dq7 valid (program, w controlled) 10 10 m s t whq7v2 (2) write enable high to dq7 valid (block erase, w controlled) 1.0 30 1.0 30 sec t ehq7v1 (2) chip enable high to dq7 valid (program, e controlled) 10 10 m s t ehq7v2 (2) chip enable high to dq7 valid (block erase, e controlled) 1.0 30 1.0 30 sec t q7vqv q7 valid to output valid (data polling) 30 35 ns t whqv1 write enable high to output valid (program) 10 10 m s t whqv2 write enable high to output valid (block erase) 1.0 30 1.0 30 sec t ehqv1 chip enable high to output valid (program) 10 10 m s t ehqv2 chip enable high to output valid (block erase) 1.0 30 1.0 30 sec notes: 1. all other timings are defined in read ac characteristics table. 2. t whq7v is the program or erase time. 3. the temperature range C40 to 125 c is guaranteed at 70ns with high speed interface test condition and v cc = 5v 5%. table 15a. data polling and toggle bit ac characteristics (1) (t a = 0 to 70 c, C20 to 85 c, C40 to 85 c or C40 to 125 c) (3) 20/31 M29F040
symbol parameter M29F040 unit -120 150 v cc = 5v 10% v cc = 5v 10% standard interface standard interface min max min max t whq7v1 (2) write enable high to dq7 valid (program, w controlled) 10 10 m s t whq7v2 (2) write enable high to dq7 valid (block erase, w controlled) 1.0 30 1.0 30 sec t ehq7v1 (2) chip enable high to dq7 valid (program, e controlled) 10 10 m s t ehq7v2 (2) chip enable high to dq7 valid (block erase, e controlled) 1.0 30 1.0 30 sec t q7vqv q7 valid to output valid (data polling) 50 55 ns t whqv1 write enable high to output valid (program) 10 10 m s t whqv2 write enable high to output valid (block erase) 1.0 30 1.0 30 sec t ehqv1 chip enable high to output valid (program) 10 10 m s t ehqv2 chip enable high to output valid (block erase) 1.0 30 1.0 30 sec notes: 1. all other timings are defined in read ac characteristics table. 2. t whq7v is the program or erase time. table 15b. data polling and toggle bit ac characteristics (1) (t a = 0 to 70 c, C20 to 85 c, C40 to 85 c or C40 to 125 c) 21/31 M29F040
ai01364b e g w a0-a18 dq7 ignore valid dq0-dq6 byte address (within blocks) data output valid tavqv tehq7v tglqv twhq7v valid tq7vqv dq7 data polling (last) cycle data verify read cycle data polling read cycles last cycle of program or erase telqv figure 9. data polling dq7 ac waveforms notes: 1. all other timings are as a normal read cycle. 2. dq7 and dq0-dq6 can transmit to valid at any point during the data output valid period. 3. twhq7v is the program or erase time. 4. during erasing operation byte address must be within block being erased. 22/31 M29F040
read dq5 & dq7 at valid address start read dq7 fail pass ai01369 dq7 = data yes no yes no dq5 = 1 dq7 = data yes no figure 10. data polling flowchart read dq5 & dq6 start read dq6 fail pass ai01370 dq6 = toggle no no yes yes dq5 = 1 no yes dq6 = toggle figure 11. data toggle flowchart parameter M29F040 unit min typ max chip program (byte) 6 sec chip erase (preprogrammed) 2.5 30 sec chip erase 8.5 sec block erase (preprogrammed) 1 30 sec block erase 1.5 sec byte program 10 1500 m s program/erase cycles (per block) 100,000 cycles table 16. program, erase times and program, erase endurance cycles (t a = 0 to 70 c; v cc = 5v 10% or 5v 5%) 23/31 M29F040
ai01367 e g w a0-a18 dq6 dq0-dq5, tavqv stop toggle last cycle of program of erase valid valid valid ignore dq7 data toggle read cycle read cycle twhqv tehqv telqv tglqv data toggle read cycle figure 12. data toggle dq6 ac waveforms note: all other timings are as a normal read cycle. 24/31 M29F040
block address on a16, a17, a18 ai01368d g, a9 = v id , e = v il n = 0 wait 4s wait 100s w = v il w = v ih g = v ih read dq0 at protection address: a0, a6 = v il , a1 = v ih and a16, a17, a18 defining block a9 = v ih ++n = 25 start fail pass yes no dq0 = 1 yes no a9 = v ih wait 4s figure 13. block protection flowchart 25/31 M29F040
protect all blocks ai01371e a6, a12, a16 = v ih e, g, a9 = v ih data e, g, a9 = v id wait 4s w = v ih e, g = v ih read at unprotection address: a1, a6 = v ih , a0 = v il and a16, a17, a18 defining block (see note 1) wait 10ms wait 4s = 00h increment block n = 0 wait 4s w = v il ++n = 1000 start fail yes yes no pass no last sect. yes no figure 14. block unprotecting flowchart note: 1. a6 is kept at v ih during unprotection algorithm in order to secure best unprotection verification. during all other protection status reads, a6 must be kept at v il . 26/31 M29F040
ordering information scheme M29F040 is replaced by the new version M29F040b device are shipped from the factory with the memory content erased (to ffh). for a list of available options (speed, package, etc...) or for further information on any aspect of this device, please contact the stmicroelectronics sales office nearest to you. operating voltage f5v speed -70 70ns -90 90ns -120 120ns -150 150ns power supplies blank v cc 10% xv cc 5% package k plcc32 n tsop32 8 x 20mm option r reverse pinout tr tape & reel packing temp. range 1 0 to 70 c 3 C40 to 125 c 5 C20 to 85 c 6 C40 to 85 c example: M29F040 -70 x n 1 tr 27/31 M29F040
plcc d ne e1 e 1 n d1 nd cp b d2/e2 e b1 a1 a r 0.51 (.020) 1.14 (.045) f a2 symb mm inches typ min max typ min max a 2.54 3.56 0.100 0.140 a1 1.52 2.41 0.060 0.095 a2 C 0.38 C 0.015 b 0.33 0.53 0.013 0.021 b1 0.66 0.81 0.026 0.032 d 12.32 12.57 0.485 0.495 d1 11.35 11.56 0.447 0.455 d2 9.91 10.92 0.390 0.430 e 14.86 15.11 0.585 0.595 e1 13.89 14.10 0.547 0.555 e2 12.45 13.46 0.490 0.530 e 1.27 C C 0.050 C C f 0.00 0.25 0.000 0.010 r 0.89 C C 0.035 C C n32 32 nd 7 7 ne 9 9 cp 0.10 0.004 drawing is not to scale. plcc32 - 32 lead plastic leaded chip carrier, rectangular 28/31 M29F040
tsop-a d1 e 1 n cp b e a2 a n/2 d die c l a1 a symb mm inches typ min max typ min max a 1.20 0.047 a1 0.05 0.15 0.002 0.007 a2 0.95 1.05 0.037 0.041 b 0.15 0.27 0.006 0.011 c 0.10 0.21 0.004 0.008 d 19.80 20.20 0.780 0.795 d1 18.30 18.50 0.720 0.728 e 7.90 8.10 0.311 0.319 e 0.50 - - 0.020 - - l 0.50 0.70 0.020 0.028 a 0 5 0 5 n32 32 cp 0.10 0.004 drawing is not to scale. tsop32 normal pinout - 32 lead plastic thin small outline, 8 x 20mm 29/31 M29F040
tsop-b d1 e 1 n cp b e a2 a n/2 d die c l a1 a symb mm inches typ min max typ min max a 1.20 0.047 a1 0.05 0.17 0.002 0.006 a2 0.95 1.05 0.037 0.041 b 0.15 0.27 0.006 0.011 c 0.10 0.21 0.004 0.008 d 19.80 20.20 0.780 0.795 d1 18.30 18.50 0.720 0.728 e 7.90 8.10 0.311 0.319 e 0.50 C C 0.020 C C l 0.50 0.70 0.020 0.028 a 0 5 0 5 n32 32 cp 0.10 0.004 drawing is not to scale. tsop32 reverse pinout - 32 lead plastic thin small outline, 8 x 20mm 30/31 M29F040
information furnished is believed to be accurate and reliable. however, stmicroelectronics assumes no responsib ility for the cons equences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of stmicroelectronics. specifications mentioned in this publicati on are subject to change without notice. this publication supersedes and replaces all information previously supplied. stmicroelectronics product s are not authorized for use as critical components in life support devices or systems without express written approval of stmicroelectro nics. the st logo is a registered trademark of stmicroelectronics ? 1999 stmicroelectronics - all rights reserved all other names are the property of their respective owners. stmicroelectronics group of companies australia - brazil - china - finland - france - germany - hong kong - india - italy - japan - malaysia - malta - morocco - singapore - spain - sweden - switzerland - united kingdom - u.s.a. http://www.st.com 31/31 M29F040

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